1. Field of the Invention
The present invention relates to a semiconductor memory device containing a switching means and a storage means, specifically, a semiconductor memory device which can be reduced in size by constructing the switching means using a diode.
2. Discussion of Related Art
In general, the size of the unit cell of the semiconductor decreases with the increase of its integrity. So far decreasing the size of the unit cell has proceeded according to the development of manufacturing apparatus and techniques. As a result of recent development, present manufacturing processes are now producing devices with line widths below half .mu.m.
FIG. 1 is a sectional view of a conventional semiconductor memory device.
The conventional semiconductor memory device has transistors serving as the switching means, and capacitor serving as storage devices. The transistor is constructed in a manner that a well 12, in which N type impurity ions are doped, and a field oxide layer 13 are formed on a semiconductor substrate 11. The field oxide layer 13 is made by local oxidation of silicon (LOCOS) or shallow trench isolation (STI). P type impurity ions are heavily doped on the active regions of a device, defined by the field oxide layer 13 and well 12, to form the bit line junction 19 and the node junction 20, serving as the source and the drain respectively. The bit line junction 19 is electrically connected to the bit line (not shown) while the node junction 20 is connected to the capacitor. Gate electrode 17 is constructed to serve as a word line by interposing gate insulating layer 15 between the bit line junction 19 and the node junction 20 on well 12. The gate insulating layer 15 is made of an oxide of silicon by the thermal oxidation, and the gate electrode 17 is made of polycrystal silicon or polycide in which impurity ions are doped. An interlevel insulating layer 21 is formed on the thus-structured transistor.
The capacitor has a storage electrode 25, constructed to make contact with node junction 20 through contact hole 23 in patterning the interlevel insulating layer 21; a dielectric layer 27, formed on the storage electrode 25; and a plate electrode 29, formed on the surface of dielectric layer 27. Storage electrode 25 fills contact hole 23, and thus makes contact with the node junction 20. storage electrode 25 and plate electrode 29 are made of polysilicon or metal in which impurity ions are doped. Dielectric layer 27 is a thin layer made of heavily dielectric materials such as silicon oxide, silicon nitride/silicon oxide, PZT(Pb(Zr Ti)O.sub.3), BST(Ba(Sn Ti)O.sub.3), or Ta.sub.2 O.sub.5, thereby storing electric charges.
The thus-structured semiconductor memory device has a channel for electrically connecting bit line junction 19 to node junction 20, on the well under the gate electrode 17, and is activated by applying a negative turn-on voltage to gate electrode 17. Therefore, when an electric charge is applied to the bit line, the electric charge accumulates on the dielectric layer 27 of the capacitor through bit line junction 19, channel, and node junction part 20. The electric charges that accumulate on the dielectric layer 27 are stored in the gate storage 17 for a predetermined time with cutting off of the turn-on voltage. In addition, when applying a negative turn-on voltage to gate electrode 17 and the negative voltage to the bit line in the state that the electric charges are accumulated, the electric charge of the dielectric layer 45 in the capacitor flow across the node junction part 20, channel and the bit line junction part 29 to the bit line.
But, the above-mentioned conventional semiconductor memory device has a problem when a transistor is used for the switching device, that this limits the ability to decrease the size of the cell because the node and bit line junctions must be formed on either side of the gate electrode. In addition, as the gate electrode is shortened to increase its integrity, the manufacturing processes become more difficult.